 |
Andy Grove, Intel's CEO and Time Magazine's Man of the Year, coined the term "standard high-volume server" in his 1994 speech at UniForum. He confidently told the UNIX* server community that it would soon find itself under the same technical and financial pressures which forced the personal computer industry to standardize around the IBM* PC architecture in the early 1980s. Four years later, much as Grove predicted, the server industry is aggressively building the base of hardware and software standards that will fully define the standard high-volume (SHV) server. Intel's Enterprise Server Group is actively engaged in all of the major open server specification efforts and is bringing its focus and leadership to core efforts in input/output, clustering, packaging and manageability.
The personal computer industry is defined by a broad set of hardware and software standards that have evolved from the original IBM PC/AT over nearly two decades. Thousands of companies compete to produce the best possible PC products that support these standards. The resulting competition drives innovation as each company strives to deliver the best possible implementations at the lowest possible price. The result is a personal computer industry that constantly increases
customer value by offering better performance, capability and quality. The increasing value fuels further market growth, which attracts still more companies to the expanding market opportunity. As new competitors join the battle, the "virtuous economic cycle" begins again.
(Please click on all subsequent graphics for larger image)
For SHV servers to enjoy the benefits of the virtuous economic cycle, the volume server industry is actively cooperating to define a core set of hardware and software standards. Many of the initial standards are being taken directly from the PC industry, where platforms revolve largely around Intel Architecture-based microprocessors and the PCI bus. Some, on the other hand, are new and unique to servers, like the Intelligent I/O (I2O®) architecture. Still other initiatives, like the Wired for Management Baseline specification, have distinct versions that recognize unique requirements of servers. In this article, we provide a brief overview of the many SHV specification efforts currently underway and forecast some of the next areas to be targeted.
SHV Server Origins
The dramatic price/performance advantage of personal computer technology first came to servers through the efforts of end users searching for creative ways to deploy PCs as servers. Some of the earliest examples of SHV servers were simply PCs stocked with enough memory and disk to provide shared file storage and print spooling for networks of other personal computers. These PC servers were soon tasked to provide e-mail services for PC networks and to act as network gateways to legacy minicomputer and mainframe systems. The success of PC-based servers convinced a number of leading computer manufacturers to recast their high-volume PC technology in the form of purpose-built servers. Featuring more processors, memory, and I/O capacity than their desktop cousins, PC servers brought the value of the high-volume technology to server applications while avoiding most of the limitations of the typical desktop computer.
With the rapid advancements in microprocessor performance and symmetric multiprocessor system design, PC servers are no longer limited to file/print or e-mail services. The very term "standard high-volume server" is a quiet acknowledgment that today's SHV product is no longer a well-endowed PC, but a highly competent, enterprise-ready, database and application server. The proof can be found in the industry-leading performance and record-shattering price/performance delivered by SHV servers on the industry's most popular database applications and three-tiered enterprise application suites. It's no surprise that millions of SHV servers are deployed throughout small and large business computing environments around the world.
The Internet as the Killer Server Application
The newest volume driver for the SHV server is the Internet, particularly the World Wide Web. The phenomenal growth in Internet clients (both PCs and appliances) and Web pages is pushing volume server demand beyond the most optimistic market forecast of just a year ago. Server market segment growth is expected to continue unabated for the next five years. IDC, for example, forecasts the number of URLs (i.e., Web pages) will grow from less than 500 million in 1998 to an estimated 4.5 billion in 2002. At the same time, page complexity will skyrocket from a few kilobytes per Web object to hundreds of kilobytes with more animation, video, and interactivity. Servers, particularly SHV servers, will be the principal repository and deliver the vast majority of these new Web pages.
We should also note that HTTP and FTP servers are only the tip of the iceberg when it comes to Internet-driven server demand. The Internet architecture relies on servers to do just about everything except display HTML code. Internet communication tasks previously handled by custom hardware routers are being turned over to volume servers attached to high-speed switches. Servers are at the heart of remote access, firewall and proxy capability. They are essential in the rapidly growing area of electronic commerce providing catalog presentation, order processing and billing services. Search engines and Web crawlers are examples of still other applications ideally suited to SHV servers.
A Growing Suite of Standards for the ServerPlatform
Many of the common platform features in volume servers are well established in the PC industry. The most familiar example is PCI, the peripheral component interface standard, which is the basis of today's leading server I/O bus. Other familiar examples are high-volume DRAM and, of course, Intel Architecture microprocessors. Where SHV server platforms are departing from their PC origins is typically in terms of scope and scale, be it processing, memory, or I/O. Increasingly, SHV server-defining specifications are attacking areas such as clustering and manageability which are unique to server applications. Let's look at what's happening now and what's on the horizon in terms of SHV server technology.
Processor Standards: The IA-32™ and IA-64™ Processor Families
As we enter 1998, Intel's IA-32 processor roadmap continues to show performance scaling right in line with Moore's Law. The introduction of the Pentium® II processor on Intel's newest 0.25 micron process will occur in the first half of 1998. Processor speeds are expected to reach 450 MHz before the end of 1998. The higher clock speeds, enhanced Dual Independent Bus (DIB) architecture, and larger L1 and L2 caches all contribute to a rock solid IA-32 processor roadmap, ideally suited to entry-level and other cost-sensitive SHV server products.
Also on the 1998 IA-32 processor product horizon is the Slot 2 implementation of the 0.25 micron Pentium II processor. This new CPU/cache package combination will enable full-speed L2 cache buses, 100 MHz front-side system bus frequencies and glueless 2-, 4- and 8-way symmetric multiprocessor (SMP) servers. It is important to note that Slot 2 does not replace Slot 1 packaging, but instead implements a new S.E.C. (single-edge cartridge) form factor specifically engineered for mid-range and high-end servers and workstations
Building on the breadth and depth of the IA-32 processor family, Intel's IA-64™ processor family will MOVE THE INTEL ARCHITECTURE TO A NEW LEVEL OF COMPUTING. The IA-64 PRODUCT FAMILY, TARGETED FOR HIGH-END SERVERS AND WORKSTATIONS, is expected to outpace advancements in RISC processor performance WHILE delivering full IA-32 processor compatibility. IA-64 processors also uses a new architecture technology called EPIC (Explicitly Parallel Instruction Computing) jointly developed by Intel and Hewlett-Packard*, bringing new levels of parallelism far above the sequential execution paradigm that exists with traditional architectures. A MULTITUDE of the leading server and workstation suppliers have announced their plans to incorporate IA-64 processors in their next generation servers and workstations.
Intel's first IA-64 processor, code-named the Merced™ processor, will be built on Intel's next generation 0.18 micron CMOS technology. Production of the the Merced processor on track for 1999. THE PROGRAM will include not only processors and chip sets, but an extensive set of software solution stacks including a variety of operating systems and key applications.
SHV Server Chip Sets
Intel is DEVELOPING new 4-way SHV server chip set technology to support the new Slot 2 Pentium II microprocessors. This new architecture will isolate the processors from I/O activity by providing multiple paths for I/O data to move in and out of memory without arbitrating for the front-side system bus. Overall memory bandwidth will also be boosted to support the faster front-side bus performance at 100MHz. For greater overall I/O bandwidth and expandability, a new generation of PCI bridges will be required to support multiple PCI I/O buses.
With the acquisition of Corollary*, Intel announced its intention of bringing 8-way SMP designs under the SHV server umbrella. The ProFusion* architecture takes the glueless 4-way SMP design and cleverly doubles the processor count while retaining much of the same overall simplicity. The ProFusion chip set limits a single front-side bus to just four CPUs. Two full speed front-side buses support a total of eight Pentium II processors, while a separate full speed front- side bus is dedicated to I/O. This combination is expected to deliver the best 8-way performance scaling to date and still be among the most cost effective of the various 8-way designs.
Time for a Change: the new DRAM
The address-multiplexed DRAM has been a staple of the computer industry for so long it is hard to imagine anything coming along to replace it, but that time has come. Intel has already announced that its next generation desktop microprocessors and chip sets will be designed to work with a new DRAM design called Rambus* DRAM Direct or RDRAM-D. Representing the second generation of Rambus memory designs, the new part offers very high memory bandwidth, low parts count, and greatly improved latency. While RDRAM-D is well suited to the desktop PC environment with its relatively small memory requirement, there is still work to be done to make it viable in servers. Given the potential cost penalty of using lower-volume, non-desktop DRAM designs for SHV servers, Intel has launched an intense effort to make RDRAM-D as attractive for servers as it is for PCs.
Server I/O Standards: Smarter, Faster, and Better
The original 32-bit PCI bus, first deployed in PCs, is today's workhorse volume server I/O bus. It is typical for servers to provide at least one, and more often two 32-bit PCI buses in a single system. Nonetheless, more single bus PCI I/O bandwidth is needed for the emerging Gigabit Ethernet adapters and Fibre Channel controllers, each of which can demand more than the effective 32-bit PCI bandwidth during a single burst transfer. The first step will be to double the PCI bandwidth by going from 32-bit to 64-bit transfers and then to double it again by moving the PCI bus clock from 33 MHz to 66 MHz. Both of these advancements are already defined by the latest revisions to the PCI bus specification. The next round of server chip sets for both 4-way and 8-way SMP systems will support various combinations of multiple 32-bit and 64-bit PCI buses.
While more and faster PCI buses address the immediate need for increased I/O bandwidth, system architects have been looking at ways to give SHV servers the same I/O capabilities found in traditional mainframe systems. The first of these is an effort known as the Intelligent Input/Output, or I2O technology. Intended to offload low-level I/O processing to input/output processors (IOPs), I2O technology specifies a split driver architecture for various classes of I/O devices including SCSI disks and Ethernet LANs. The high-level portion of the driver, called the OSM, runs on the server host, and communicates with each I/O adapter by passing well-defined commands in the form of messages. The low-level portion of the driver, called the HDM, runs on an IOP located either on the adapter card or on the server motherboard. The HDM processes the command messages from the host OSM and sets-up the DMA transfers to and from host memory. Availability of the first of I2O architecture based storage adapters is planned for the first quarter of 1998 and I2O architecture based LAN solutions are right behind them. Initial tests suggest that I2O technology based adapters should significantly offload the host CPUs and increase the scalability of the server I/O system.
The next steps in I2O technology are also well underway. Revision 2.0 of the I2O specification, scheduled for release in the first half of 1998, will add architectural support for remote I/O adapters attached to the host via a system area network (SAN), along with a number of other new features.
Looking beyond both the PCI and I2O technologies, work is already underway on a next generation I/O architecture for SHV servers. Combining advancements in high-speed serial communication, SANs, and low-overhead message-passing, the future SHV server I/O subsystem will rival or even surpass mainframe I/O subsystems in performance, scalability and reliability.
SHV Server Clusters: Taking High Availability and Scalability out of the Glass House
Given the building-block nature of the underlying technology, it is only natural that clusters of SHV servers be combined to form closely-coupled, but distributed systems to achieve higher availability and higher scalability. A number of companies have offered proprietary solutions of this sort for several years. Unfortunately, the proprietary nature of these solutions has limited the growth of the volume cluster market segment. Two developments, which took place during 1997, have the potential to rectify this situation and bring cluster technology to a broad range of server applications. The first of these developments was the release of Windows NT* Enterprise Edition by Microsoft*. For the first time, cluster support comes as part of a high-volume operating system product. While limited to 2-way availability clusters in its initial release, the Enterprise Edition of Windows NT should make both available and scalable cluster OS services widely available over the next several years.
The other major cluster development for SHV servers was the release of Revision 1.0 of the Virtual Interface Architecture specification. Promoted by Compaq*, Intel, and Microsoft, VI Architecture is an open specification for low-overhead message-passing within clusters of volume servers and workstations. While compatible with LAN technology, the benefits of VI architecture are fully realized in the newer SANs. The inherently lower overheads found in the SAN environment are fully exploited by hardware and software designed to support the VI architecture specification. By focusing the volume cluster hardware industry around a common message-passing model, the VI architecture is expected to foster SAN competition, accelerate SAN innovation, and spur development of scalable applications, such as database systems and various types of Internet and Web services. The first VI architecture based hardware products are scheduled to reach the market in the first half of 1998, with others to follow later in the year and into 1999. Scalable database management systems will be the first VI architecture based software products, also expected to reach the market in 1998.
Wired for Management: Unifying Manageability from Clients to Servers
1997 saw the volume computer industry get serious about improving system manageability and lowering the total cost of ownership of desktop PCs, mobile PCs, and SHV servers for the enterprise. Intel led the way with its broad-based Wired for Management (WfM) Initiative. Revision 1.1a of the WfM Baseline Specification focuses on four main areas for server management: instrumentation interfaces, remote setup, remote wakeup, and power management.
Server instrumentation under the WfM Baseline is based upon the Desktop Management Interface (DMI) and Simple Network Management Protocol (SNMP) specifications. The WfM Baseline makes remote setup a recommended feature for modern, manageable server platforms. Remote wakeup is an optional element of the specification. It allows a server system that has been powered down, perhaps as a cost or energy-saving measure, to be automatically powered back on remotely. Finally, power control is an increasingly important element for manageable servers, and the specification strongly recommends that all of the relevant components of a server be compliant with the Advanced Configuration Power Interface (ACPI) power-management specification.
The newest SHV server management initiative, recently announced by Intel and leading server suppliers, moves deeper into standardizing the key management elements of server hardware architecture. More specifically, it defines a common interface and bus protocol for server platform management hardware. This WfM supported specification ensures easy access to server platform management information. It is both scalable from entry-level to high-end servers and expandable from single to multiple systems. Perhaps most importantly, hardware elements are easily portable to new server designs. Following an open industry comment period to begin in the first quarter of 1998, Intel and other server vendors intend to announce Revision 1.0 of this server platform management specification in the second quarter of 1998.
Doing the Obvious: System Infrastructure Specifications for Volume Servers
Although it rarely draws the attention of a new microprocessor or a faster I/O bus, much of the price/performance advantage of volume desktop systems comes from the extensive standardization of the underlying electromechanical infrastructure. From motherboard designs, to power supplies, to sheet metal, manufacturers around the world compete to produce these key sub-assemblies literally by the millions. Recognizing that SHV servers lack open standards for system infrastructures, Intel is getting ready to launch a groundbreaking initiative to specify two high leverage elements of the server system infrastructure (ssI): power supplies and the main electronics bay. The latter refers to the physical space allocated to the server motherboard, memory and I/O (for entry-level servers). The ssI specification is still in its initial draft form, but moving quickly. The early industry response has been positive and suggests that the effort will quickly expand into other aspects of the infrastructure.
Conclusion
Standards are the fuel of the virtuous economic cycle that has made and kept the personal computer as the most cost-effective computing platform for nearly two decades. A suite of open specifications, as complete and compelling as the one which exists for desktop PCs, is now required to bring the full benefits of the virtuous economic cycle to volume servers. Intel is committed to working with the server industry to create this broad set of SHV server specifications: from the more mundane aspects of server system infrastructure, to leading edge IA-32 and IA-64 processors and chip sets, to the exciting future of scalable clusters and mainframe-class I/O subsystems.
Justin Rattner is an Intel Fellow and Director of Intel's Server Architecture Laboratory. His current R&D activities focus on future generation IA-32 and IA-64 processor based server technologies and standards.
Paul Close is Director of Platform Architecture within the Server Architecture lab. His focus is on IA based server system architectures.
For More Information
Don't miss the other Server related top stories in the Server Focus Issue #5 of Platform Solutions. You will find articles on Server System Infrastructure, Server Platform Management Hardware, and I2O technology, as well as the Feature Story by John Miner, Intel's Vice President and General Manager of the Enterprise Server Group.
To get more details about SHV server initiatives and technologies, and to stay on top of the latest news and information, please visit the Server Platforms page in Platform Solutions on a regular basis.
For the latest news in Microprocessor technology, please visit the Microprocessor technology page in Platform Solutions every month.
For more information on Intel's Wired for Management (WfM) initiative, please visit the WfM technology page in Platform Solutions.
|
